Portale di Ateneo - En.Unibs.it

COMPUTER ORGANIZATION AND DESIGN

Single discipline educational activity

Course Sheet

Academic Year of enrolment:

2012/2013

Academic Year of provision:

2013/2014

Type of Course:

Characterising

Degree:

Bachelor's Degree Programme in COMPUTER SCIENCE AND ENGINEERING

Disciplinary Sector:

Data Processing Systems

Language:

Italian

Grouping type:

Credits:

Programme Year:

Professor and Collaborators:

GIACOMIN Massimiliano Professor

Cycle:

Second semester

Hours of classroom activity:

Hours of individual study:

Binary information representation. Basic notions of computer organization. Basic knowledge of C language.

Educational Goals

This course provides the fundamental notions about modern computer (hardware and software) organization and design. Referring to real examples (including MIPS and INTEL processors), the course introduces assembly language, control design and implementation of a multicycle and pipelined processor, memory hierarchy and the basics of Input-Output management. Specific attention will be devoted to the performance evaluation of a computer system.

Content

Instruction Set Architecture (ISA) - Machine language - Assembly language
Combinational logic
Sequential logic
Memory elements, registers and interconnection.
The processor: datapath and control
Pipelining
Memory hierarchy

Extended Syllabus

Introduction
Von Neumann architecture - Technologies for building processors and memories
Assembler
Instruction Set Architecture (ISA) - Machine language - Assembly language - MIPS Assembly language - Intel Assembly language (introduction).
Combinational logic
Truth tables and combinational circuits - Gates - Boolean Algebra - Logic functions and canonical forms - PLA and ROM implementation - Examples: encoder, decoder, multiplexor, adder, Arithmetic Logic Unit (ALU)
Sequential logic
Flip-Flops and latches - Clocking methodology - Finite state machines (Moore machine and Mealy machine) - Implementation
Memory elements
Registers - Register file - Memory typologies - SRAM - DRAM
The processor: datapath and control
Single-cycle implementation (datapath and control unit) - Multi-cycle implementation - Microprogramming - Exception - Performance evaluation
Pipelining
Pipelined datapath and pipelined control - Structural hazards - Data hazards, stalls and forwarding - Control hazards, delayed branch, static and dynamic branch prediction - Performance evaluation with hazards - Advanced pipelining: static and dynamic multiple-issue (introduction).
Memory hierarchy
Principle of locality - Cache memory (direct-mapped cache, set-associative cache, multilevel cache) - Hit/miss rate - Miss penalty - Accessing a cache (write-through and write-back) - Performance evaluation - Introduction to virtual memory
Input/Output
I/O devices management